ASAP 2017 - The 28th Annual IEEE International Conference on
Application-specific Systems, Architectures and Processors

July 10th-12th 2017, Seattle, WA, USA

Preliminary Program Overview

Monday July 10th
08:00 - 09:00Breakfast and Registration
09:00 - 09:10Welcome and Opening Remarks
09:10 - 10:30Paper Session 1 - Machine Learning
 Session Chair - Jason Anderson
10:30 - 11:00Coffee Break
11:00 - 12:00Keynote: Tim Sherwood, UC Santa Barbara
 Performance is Overrated or: How I Stopped Worrying and Learned to Love Slow Hardware
12:00 - 13:30Lunch
13:30 - 15:30Paper Session 2: Security
 Session Chair - Ken Eguro
15:30 - 16:30Poster Session 1
16:30 - 17:20Paper Session 3: Image Processing
 Session Chair - Darshika G. Perera
18:30 - 21:00Reception
  
Tuesday July 11th
08:00 - 09:00Breakfast and Registration
09:00 - 10:30Paper Session 4 - Memory/Storage
 Session Chair - Arslan Munir
10:30 - 11:00Coffee Break
11:00 - 12:00Keynote: David Pellerin, Amazon Web Services
 Accelerated Computing on AWS: Applications for GPUs and FPGAs
12:00 - 13:30Lunch
13:30 - 15:30Paper Session 5 - High Performance Computing
 Session Chair - Marilyn Wolf
15:30 - 16:30Poster Session 2
16:30 - 17:20Paper Session 6 - Digital Signal Processing
 Session Chair - Chun-Jen Tsai
  
Wednesday July 12th
08:00 - 09:00Breakfast and Registration
09:00 - 10:15Paper Session 7 - Control Systems and Parallel Programming Languages
 Session Chair - Phillip Jones
10:15 - 11:00Poster Session 3
11:00 - 12:00Panel Discussion: Industry and Academic Collaboration
 Cisco Systems: Yousef S. Iskander, Technical Leader, Advanced Security Research Group
Micron: John Watson, Director, Marketing and Business Development
Microsoft: Derek Chiou, Partner Engineering Manager, Microsoft Azure Cloud Silicon
Xilinx: Ramine Roane, Senior Director, Product Planning
12:00 - 12:15Best Paper Announcement and Closing Remarks

Detailed Preliminary Program

Monday July 10th
08:00 - 09:00Breakfast
09:00 - 09:10Welcome and Opening Remarks
09:10 - 10:30Paper Session 1 - Machine Learning
Session Chair - Jason Anderson
 CATERPILLAR: Coarse Grain Reconfigurable Architecture for Accelerating the Training of Deep Neural Networks
 Yuanfang Li and Ardavan Pedram
 Stanford University and Cerebras Systems
 slides
 Fast and Efficient Implementation of Convolutional Neural Networks on FPGA
 Abhinav Podili, Chi Zhang and Viktor Prasanna
 University of Southern California
 slides
 Parallel Multi Channel Convolution using General Matrix Multiplication - Short Paper
 Aravind Vasudevan, Andrew Anderson and David Gregg
 Trinity College Dublin
 slides
 A Fast FPGA Implementation for Adaptive Independent Component Analysis - Short Paper
 Mahdi Nazemi, Shahin Nazarian and Massoud Pedram
 University of Southern California
 slides
10:30 - 11:00Coffee Break
11:00 - 12:00Keynote: Tim Sherwood, UC Santa Barbara
 Performance is Overrated or: How I Stopped Worrying and Learned to Love Slow Hardware
12:00 - 13:30Lunch
13:30 - 15:30Paper Session 2: Security
Session Chair - Ken Eguro
  Design and Comparative Evaluation of GPGPU- and FPGA-based MPSoC ECU Architectures for Secure, Dependable, and Real-Time Automotive CPS
 Bikash Poudel, Naresh Giri and Arslan Munir
  University of Nevada, Reno
 High-Level Synthesis for Side-Channel Defense
 Sven Tenzing Choden Konigsmark, Deming Chen and Martin Wong
 University of Illinois at Urbana-Champaign
 slides
 DoSGuard: Protecting Pipelined MPSoCs Against Hardware Trojan Based DoS Attacks
 Amin Malekpour1, Roshan Ragel2, Aleksandar Ignjatovic1 and Sri Parameswaran1
 1University of New South Wales, 2University of Peradeniya
 slides
 Hardwiring the OS Kernel into a Java Application Processor
 Chun-Jen Tsai, Cheng-Ju Lin, Cheng-Yang Chen, Yan-Hung Lin, Wei-Jhong Ji and Sheng-Di Hong
 National Chiao Tung University
 slides
 Hardware Support for Embedded Operating System Security - Short Paper
 Arman Pouraghily, Tilman Wolf and Russell Tessier
 University of Massachusetts, Amherst
 slides
15:30 - 16:30Poster Session 1
 DeepPump: Multi-Pumping Deep Neural Networks
 Ruizhe Zhao, Tim Todman, Wayne Luk and Xinyu Niu
 Imperial College London
 Efficiency in ILP Processing by Using Orthogonality
 Marcel Brand, Frank Hannig, Alexandru Tanase and Jürgen Teich
 Friedrich-Alexander University Erlangen-Nürnberg
 A Fast and Accurate Logarithm Accelerator for Scientific Applications
 Jing Chen and Xue Liu
 McGill University
 Model Checking Cloud Rendering System for the QoS Evaluation
 Haoyu Liu, Huahu Xu, Honghao Gao, Minjie Bian and Danqi Chu
 Shanghai University
 Plus posters for short papers from Paper Sessions 1 & 2
16:30 - 17:20Paper Session 3: Image Processing
Session Chair - Darshika G. Perera
 Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter
 Stefan Tabel1, Korbinian Weikl1 and Walter Stechele2
 1Semiconductor Laboratory of the Max Planck Society, 2Technical University of Munich, Chair of Integrated Systems
 slides
 Real-time Object Detection in Software with Custom Vector Instructions and Algorithm Changes
 Joe Edwards and Guy Lemiuex
 University of British Columbia
 slides
18:30 - 21:00Reception
  
Tuesday July 11th
08:00 - 09:00Breakfast
09:00 - 10:30Paper Session 4 - Memory/Storage
Session Chair - Arslan Munir
 An Efficient Embedded Multi-Ported Memory Architecture for Next-Generation FPGAs
 S. Navid Shahrouzi and Darshika G. Perera
 University of Colorado at Colorado Springs
 slides
 A Staged Memory Resource Management Method for CMP Systems
 Yangguo Liu, Junlin Lu, Dong Tong and Xu Cheng
 Microprocessor Research & Development Center, Peking University
 slides
 CFStore: Boosting Hybrid Storage Performance by Device Crossfire
 Wei Zhou, Dan Feng and Zhipeng Tan
 School of Computer Science and Technology, Wuhan National Laboratory for Optoelectronics
 slides
 RVNet: a Fast and High Energy Efficiency Network Packet Processing System on RISC-V - Short Paper
 Yanpeng Wang, Mei Wen, Chunyuan Zhang and Dong Chen
 National University of Defense Technology and National Key Laboratory for Parallel and Distributed Processing
10:30 - 11:00Coffee Break
11:00 - 12:00Keynote: David Pellerin, Amazon Web Services
 Accelerated Computing on AWS: Applications for GPUs and FPGAs
 slides
12:00 - 13:30Lunch
13:30 - 15:30Paper Session 5 - High Performance Computing
Session Chair - Marilyn Wolf
 Massive Spatial Query on the Kepler Architecture
 Yili Gong, Jia Tang and Wenhai Li
 State Key Laboratory of Software Engineering, Wuhan University
 slides
 PFSI.sw: A Programming Framework for Sea Ice Model Algorithms Based on Sunway Many-core Processor
 Binyang Li1, Bo Li2 and Depei Qian1
 1Beihang University, 2BUAA
 slides
 MicRun: A Framework for Scale-free Graph Algorithms on SIMD Architecture of the Xeon Phi
 Jie Lin, Yusong Tan, Qingbo Wu and Xiaoling Li
 National University of Defence Technology
 slides
 Hierarchical Dataflow Model for Efficient Programming of Clustered Many-Core Processors - Short Paper
 Julien Hascoët12, Karol Desnos23, Jean-François Nezan23 and Benoît Dupont de Dinechin1
 1Kalray, 2INSA de Rennes, 3IETR
 slides
 Modeling and Evaluation for Gather/Scatter Operations in Vector-SIMD architectures - Short Paper
 Hongbing Tan, Sheng Liu and Haiyan Chen
 National University of Defense Technology
 slides
 reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements - Short Paper
 Achim Lösch and Marco Platzner
 Paderborn University
 slides
15:30 - 16:30Poster Session 2
 High-throughput Area-efficient Processor for 3GPP LTE Cryptographic Core Algorithms
 Huo Yuanhong1 and Dake Liu2
 1Beijing Institute of Technology, 2Linkoping University
 KV-FTL: A Novel Key-Value Based FTL Scheme for Large Scale SSDs
 Juan Li, Zhengguo Chen, Zhiguang Chen, Nong Xiao and Fang Liu
 National University of Defense Technology
 Plus posters for short papers from Paper Sessions 4 & 5
16:30 - 17:20Paper Session 6 - Digital Signal Processing
Session Chair - Chun-Jen Tsai
 Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing
 Akif Oezkan, Oliver Reiche, Frank Hannig and Jürgen Teich
 Friedrich-Alexander University Erlangen-Nürnberg
 slides
 High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC Screen Content Coding extension - Short Paper
 Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P.M.K. Tharaka, Geethan Karunaratne, R.M.A.U. Senarath, Ishantha Perera, Ashen Ekanayake and Ajith Pasqual
 Paraqum Technologies
 slides
 Design and Implementation of Adaptive Signal Processing Systems Using Markov Decision Processes - Short Paper
 Lin Li1, Adrian Sapio1, Jiahao Wu1, Yanzhou Liu1, Kyunghun Lee1, Marilyn Wolf2 and Shuvra Bhattacharyya3
 1University of Maryland, 2Georgia Institute of Technology, 3Tampere University of Technology, Finland
 slides
  
Wednesday July 12th
08:00 - 09:00Breakfast
09:00 - 10:15Paper Session 7 - Control Systems and Parallel Programming Languages
Session Chair - Phillip Jones
 An Embedded Scalable Linear Model Predictive Hardware-based Controller using ADMM
 Pei Zhang, Joseph Zambreno and Phillip Jones
 Iowa State University
 slides
 CGRA-ME: A Unified Framework for CGRA Modelling and Exploration - Short Paper
 S. Alexander Chin1, Noriaki Sakamoto2, Allan Rui1, Jim Zhao1, Jin-Hee Kim1, Yuko Hara Azumi2 and Jason Anderson1
 1University of Toronto, 2Tokyo Institute of Technology
 slides
 OpenCL-Based Design Pattern for Line Rate Packet Processing - Short Paper
 Jehandad Khan1, Peter Athanas1, Skip Booth2 and John Marshall2
 1Virgina Tech, 2Cisco Systems
 slides
 Acceleration of Frequent Itemset Mining on FPGA Using SDAccel and Vivado HLS - Short Paper
 Vinh Dang and Kevin Skadron
 University of Virginia
 slides
 OpenMP Device Offloading to FPGA Accelerators - Short Paper
 Lukas Sommer, Jens Korinth and Andreas Koch
 TU Darmstadt
 slides
10:15 - 11:00Poster Session 3
 Posters for short papers from Paper Sessions 6 & 7
11:00 - 12:00Panel Discussion: Industry and Academic Engagements
 Cisco Systems: Yousef S. Iskander, Technical Leader, Advanced Security Research Group slides
 Micron: John Watson, Director, Marketing and Business Development slides
 Microsoft: Derek Chiou, Partner Engineering Manager, Microsoft Azure Cloud Silicon slides
 Xilinx: Ramine Roane, Senior Director, Product Planning slides
12:00 - 12:15Closing Remarks

Keynote and Panel Discussion Details

Keynote 1
Tim Sherwood, UC Santa Barbara - Performance is Overrated or: How I Stopped Worrying and Learned to Love Slow Hardware

Abstract: Processor performance has doubled many many times over during the past 40 years, but the very techniques used to achieve these performance gains have made it increasingly difficult to build software systems with critical properties such as security, determinism, real-time, non-interference, debuggability, and correctness. As we continue our march towards increasingly complex and heterogeneous chips, with more and more hidden state (e.g., predictors, caches, modes, accelerators), these properties are only becoming harder to realize. This fact significantly impedes progress in the development of our most safety-critical embedded systems such as those found in medical, avionic, and automotive systems. What if we started from scratch? What if we reconsidered system architecture from the gates up with an eye, first and foremost, towards the properties necessary to build reliable and trustworthy computing systems? Even if, in the end, we don't want to abandon performance and/or legacy infrastructure, can the lessons learned from this "gates up" thinking then be applied in practice to existing systems? Professor Sherwood will describe his experience with this approach around two important properties (security and correctness) and his experience transitioning ideas from basic research through to practical commercial products.

Speaker Bio: Tim Sherwood is a Professor of Computer Science and the Associate Vice Chancellor for Research at UC Santa Barbara. He is a 7-time winner of the IEEE Micro Top Pick Award, the co-founder of the hardware security startup Tortuga Logic, an ACM Distinguished Scientist, winner of the UCSB Academic Senate Distinguished Teaching Award, and is the 2016 SIGARCH Maurice Wilkes Awardee "for contributions to novel program analysis advancing architectural modeling and security".

Keynote 2
David Pellerin, Amazon Web Services - Accelerated Computing on AWS: Applications for GPUs and FPGAs slides

Abstract: The availability of FPGA-accelerated cloud services, combined with improved FPGA programming tools, is enabling a new generation of reconfigurable computing researchers and commercial application developers. This keynote session provides a technical overview of the F1 FPGA cloud-based instances, and walks through a typical development and deployment process including details of the FPGA hardware interfaces and software APIs. The session also includes information about the AWS Marketplace that allows FPGA applications to be secured, distributed, and monetized.

Speaker Bio: David Pellerin is Business Development Principal for High Performance Computing at AWS, with a focus on high-scale applications in engineering, manufacturing, financial services, life sciences, media, and energy. Prior to joining AWS, Mr. Pellerin had a career in electronic design automation and FPGA-accelerated computing. He has experience with circuit simulation and synthesis, grid and cluster computing, and embedded systems. Mr. Pellerin is the author of five Prentice Hall technical books including Practical Design Using Programmable Logic and Practical FPGA Programming in C.

Panel Discussion
Industry and Academic Collaboration
Representatives from Cisco Systems, Micron, Microsoft, and Xilinx will have a short presentation about their latest university program offerings. We will then discuss topics such how to best engage as an academic, what they expect a good research group to do, how to share results, etc.
Cisco Systems: Yousef S. Iskander, Technical Leader, Advanced Security Research Group slides
Micron: John Watson, Director, Marketing and Business Development slides
Microsoft: Derek Chiou, Partner Engineering Manager, Microsoft Azure Cloud Silicon slides
Xilinx: Ramine Roane, Senior Director, Product Planning slides








Important dates:
Submissions due:April 3rd
THERE WILL BE NO DEADLINE EXTENSION
Author notification:May 12th
Camera ready:June 2nd
Early registration ends:June 2nd
Apply for Student Travel Grant:June 2nd
Conference:July 10-12th